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C8051F380/1/2/3/4/5/6/7/C
17.2. Power-Fail Reset / V DD Monitor
When a power-down transition or power irregularity causes V DD to drop below V RST , the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V DD returns
to a level above V RST , the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V DD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V DD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V DD monitor is disabled by code and a software reset is performed, the
V DD monitor will still be disabled after the reset.
I mportant Note: If the V DD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the V DD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V DD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the V DD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the V DD monitor to stabilize (see Table 5.4 for the V DD Monitor turn-on time).
3. Select the V DD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for V DD monitor timing; note that the power-on-reset delay is not incurred after a V DD
monitor reset. See Table 5.4 for complete electrical characteristics of the V DD monitor.
Rev. 1.4
131
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